AMERICAN DATA AQUISITION CORPORATION
5525MF, 5550MF
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Card Type |
Data Aquisition |
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Chip Set |
Unidentified |
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Maximum Onboard Memory |
Unidentified |
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I/O Options |
Analog input, digital input |
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Hard Drives supported |
None |
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Floppy drives supported |
None |
|
Data Bus |
8-bit ISA |
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Card Size |
Full-length |
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CONNECTIONS |
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Function |
Label |
Function |
Label |
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50-pin analog/digital signals connector |
J1 |
DAC1 bipolar offset selector |
P5 |
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DACO converter gain selector |
P1 |
DAC1 unipolar offset selector |
P6 |
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DAC0 bipolar offset selector |
P2 |
A/D converter gain selector |
P7 |
|
DAC0 unipolar offset selector |
P3 |
A/D bipolar offset selector |
P8 |
|
DAC1 converter gain selector |
P4 |
A/D unipolar offset selector |
P9 |
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USER CONFIGURABLE SETTINGS |
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Function |
Label |
Position |
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|
» |
Counter 0 out hardware trigger source |
JP2 |
Pins 1 & 2 closed |
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TRIG/GATE input hardware trigger source |
JP2 |
Pins 2 & 3 closed |
|
» |
Mux address lines disabled |
W1 |
Open |
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Mux address lines enabled |
W1 |
Closed |
|
» |
Mux control lines disabled |
W2 |
Open |
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Mux control lines enabled |
W2 |
Closed |
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COUNTER SOURCE SETTINGS |
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Counter |
Setting |
Label |
Position |
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|
» |
Counter 2 clock source |
External (clock 2) |
JP1 |
Pins 2 & 3 closed |
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|
Counter 2 clock source |
1.00 MHz oscillator |
JP1 |
Pins 1 & 2 closed |
|
» |
Counter 1 clock source |
1.00 MHz oscillator |
JP3 |
Pins 1 & 2 closed |
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|
Counter 1 clock source |
External (clock 1) |
JP3 |
Pins 2 & 3 closed |
|
» |
Counter 0 gate source |
External (gate 0) |
JP4 |
Pins 2 & 3 closed |
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|
Counter 0 gate source |
Counter 1 out INV |
JP4 |
Pins 1 & 2 closed |
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POWER CONFIGURATION SELECTION |
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|
Signal |
Label |
Position |
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|
» |
Clock 2 |
JP20 |
Pins 1 & 2 closed |
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|
+12V (fused) |
JP20 |
Pins 2 & 3 closed |
|
» |
Out 2 |
JP21 |
Pins 1 & 2 closed |
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|
AGND |
JP21 |
Pins 2 & 3 closed |
|
» |
Gate 2 |
JP22 |
Pins 1 & 2 closed |
|
|
-12V (fused) |
JP22 |
Pins 2 & 3 closed |
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ERROR INTERRUPT SELECTION |
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Setting |
JP5 |
|
|
» |
Interrupt disabled |
Pins 1 & 2 closed |
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|
Software control via ADCSR0 bit 6 |
Pins 2 & 3 closed |
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|
Interrupt enabled |
Pins 3 & 4 closed |
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Note: Error conditions include clock overrun, polled I/O data overrun and DMA overrun on A/D converter. |
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DMA CHANNEL SELECTION |
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Channel |
W17 |
W18 |
W19 |
W20 |
W21 |
W22 |
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1 |
Closed |
Open |
Open |
Closed |
Open |
Open |
|
|
2 |
Open |
Closed |
Open |
Open |
Closed |
Open |
|
» |
3 |
Open |
Open |
Closed |
Open |
Open |
Closed |
|
ANALOG OUTPUT CONFIGURATION (DAC0) |
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Data Coding |
Polarity |
Range |
JP8 |
JP10 |
JP11 |
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|
» |
Two's compliment |
Bipolar |
-10V to +10V |
Pins 1 & 2 |
Pins 2 & 3 |
Pins 1 & 2 |
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|
Two's compliment |
Bipolar |
-5V to +5V |
Pins 1 & 2 |
Pins 2 & 3 |
Pins 2 & 3 |
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|
Straight/offset binary |
Unipolar |
0V to +10V |
Pins 2 & 3 |
Pins 1 & 2 |
Pins 2 & 3 |
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Note: DAC0 and DAC1 may be configured independently. Pins designated are in the closed position. |
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ANALOG OUTPUT CONFIGURATION (DAC1) |
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Data Coding |
Polarity |
Range |
JP9 |
JP12 |
JP13 |
|
|
» |
Two's compliment |
Bipolar |
-10V to +10V |
Pins 1 & 2 |
Pins 2 & 3 |
Pins 1 & 2 |
|
|
Two's compliment |
Bipolar |
-5V to +5V |
Pins 1 & 2 |
Pins 2 & 3 |
Pins 2 & 3 |
|
|
Straight/offset binary |
Unipolar |
0V to +10V |
Pins 2 & 3 |
Pins 1 & 2 |
Pins 2 & 3 |
|
Note: DAC0 and DAC1 may be configured independently. Pins designated are in the closed position. |
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ANALOG INPUT REFERENCE CONFIGURATION |
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Setting |
JP6 |
JP7 |
JP18 |
JP19 |
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|
» |
Pseudo differential (PD) |
Pins 1 & 2 |
Pins 1 & 2 |
Pins 1 & 2 |
Pins 1 & 2 |
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Single ended (SE) |
Pins 1 & 2 |
Pins 1 & 2 |
Pins 1 & 2 |
Pins 2 & 3 |
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Fully differential (DI) |
Pins 2 & 3 |
Pins 2 & 3 |
Pins 2 & 3 |
Open |
|
Note: Pins designated are in the closed position. |
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ANALOG INPUT RANGE CONFIGURATION |
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Polarity |
Range |
JP14 |
JP15 |
JP16 |
JP17 |
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|
» |
Bipolar |
-10V to +10V |
Pins 1 & 2 |
Pins 2 & 3 |
Pins 1 & 2 |
Pins 2 & 3 |
|
|
Bipolar |
-5V to +5V |
Pins 1 & 2 |
Pins 2 & 3 |
Pins 2 & 3 |
Pins 2 & 3 |
|
|
Unipolar |
0V to +10V |
Pins 2 & 3 |
Pins 1 & 2 |
Pins 2 & 3 |
Pins 1 & 2 |
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Note: Pins designated are in the closed position. |
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BASE I/O ADDRESS SELECTION |
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Setting |
W3 |
W4 |
W5 |
W6 |
W7 |
W8 |
W9 |
W10 |
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|
000h |
Open |
Open |
Open |
Open |
Open |
Open |
Open |
Open |
|
|
020h |
Open |
Open |
Open |
Open |
Open |
Open |
Open |
Closed |
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|
040h |
Open |
Open |
Open |
Open |
Open |
Open |
Closed |
Open |
|
|
060h |
Open |
Open |
Open |
Open |
Open |
Open |
Closed |
Closed |
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|
080h |
Open |
Open |
Open |
Open |
Open |
Closed |
Open |
Open |
|
» |
200h |
Open |
Open |
Open |
Closed |
Open |
Open |
Open |
Open |
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|
F60h |
Closed |
Closed |
Closed |
Closed |
Closed |
Open |
Closed |
Closed |
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|
F80h |
Closed |
Closed |
Closed |
Closed |
Closed |
Closed |
Open |
Open |
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|
FA0h |
Closed |
Closed |
Closed |
Closed |
Closed |
Closed |
Open |
Closed |
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|
FC0h |
Closed |
Closed |
Closed |
Closed |
Closed |
Closed |
Closed |
Open |
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|
FE0h |
Closed |
Closed |
Closed |
Closed |
Closed |
Closed |
Closed |
Closed |
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Note: A total of 256 base address settings are available. The jumpers are a binary representation of the decimal memory addresses. W3 is the Most Significant Bit and jumper W10 is the Least Significant Bit. The jumpers have the following decimal values: W3=4096, W4=2048, W5=1024, W6=512, W7=256, W8=128, W9=64, W10=32. Turn off the switches and add the values of the switches to obtain the correct memory address. (Close=1, Open=0) |
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IRQ INTERRUPT SELECTION |
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IRQ |
W11 |
W12 |
W13 |
W14 |
W15 |
W15 |
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|
IRQ2 |
Closed |
Open |
Open |
Open |
Open |
Open |
|
|
IRQ3 |
Open |
Closed |
Open |
Open |
Open |
Open |
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|
IRQ4 |
Open |
Open |
Closed |
Open |
Open |
Open |
|
|
IRQ5 |
Open |
Open |
Open |
Closed |
Open |
Open |
|
|
IRQ6 |
Open |
Open |
Open |
Open |
Closed |
Open |
|
» |
IRQ7 |
Open |
Open |
Open |
Open |
Open |
Open |
