M I N I P O R T 4 2 P MINISTOR
NO MORE PRODUCED Native| Translation
------+-----+-----+-----
Form PCMCIA TYPE III Cylinders 1076| 547| |
Capacity form/unform 42/ MB Heads 2| 4| |
Seek time / track 16.0/ 6.0 ms Sector/track | 38| |
Controller PCMCIA 2.01 Precompensation
Cache/Buffer 32 KB Landing Zone
Data transfer rate 2.500 MB/S int Bytes/Sector 512
5.000 MB/S ext
Recording method RLL 1/7 operating | non-operating
-------------+--------------
Supply voltage 5 V Temperature *C 5 55 | -40 70
Power: sleep 0.1 W Humidity % | 5 95
standby W Altitude km 12.192| 12.192
idle 0.5 W Shock g 150 | 200
seek 1.3 W Rotation RPM 4464
read/write 1.5 W Acoustic dBA
spin-up W ECC Bit
MTBF h 250000
Warranty Month 12
Lift/Lock/Park YES Certificates CSA,FCC,IEC950,UL1950
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F E A T U R E S
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MINISTOR PCMCIA ATA PRODUCT MANUAL 830000600 VER. 1.0 12/1993
PCMCIA ATA drive definition
---------------------------
This document describes how the MiniStor AZA Protocol mapy onto the
PCMCIA interface. It resolves and clarifies the enhancements and
restrictions which result from the use of the PCMCIA interface with
the ATA Protocol.
Differences between the ATA Standard and PCMCIA ATA
---------------------------------------------------
a) The PCMCIA ATA specification provides Ready/Busy signal which can
be used to prevent the host from accessing the drive before the
card before the card is available following a power-up, hardware
reset or PCMCIA Soft Reset.
b) The PCMCIA ATA specification provides a Soft Reset protocol.
c) The PCMCIA interface permits systems to address peripherals in
more general ways than the traditional ATA specification allows.
d) "High Impedance" state of INTRQ is replaced by interrupts
disabled state.
e) DMA is not a supported function in PCMCIA interface.
I/O accesses are constrained at the PCMCIA interface as follows:
----------------------------------------------------------------
- The host shall perform all word (16-bit) I/O accesses with A0 = 0.
- If a card return -IOIS16 as active in response to the address on
the bus then the host system is permitted to transfer 16 bits of
data to the card in a single cycle, otherwise, the host system
shall perform two 8 bit cycles: even byte then odd byte.
Addressing Modes - ATA Drive register set definition and protocol
-----------------------------------------------------------------
There are three basic addressing spaces in the PCMCIA ATA card,
Attribute Memory, Common Memory, and Common I/O.
Attribute Memory
----------------
Attribute Memory contains the Card Information Structure (CIS Area)
and the Card Configuration Registers (CCR). The information in
Attribute Memory is accessed using a memory operation that asserts
-REG, -CE1 along with the OE or -WE signals. The CIS starts at
address 0h and is 256 bytes long of Read Only Sequential Access
Memory. To be compatible with 8-bit hosts, the CIS information is
stored on even-byte boundaries (0,2,4,...). It contains configuration
information in a Metaformat, called tuples. (Tuple definitions can
be found in the PCMCIA specification.) The CCR are used by the Host
to configure the PC Card.
Card Information Structure
--------------------------
The Card Information Structure (CIS) is the cornerstone to the PCMCIA
standard. It is a variable-length chain (or linked list) of data
block or tuples. Byte 0 of each tuple contains the tuple function
code. Byte 1 contains the offset to the next tuple in the list. The
general function of the CIS is to allow the host to interrogate the
card as to its function and features. The host can then determine how
to configure its memory to accommodate or reject the card.
Card Configuration Registers
----------------------------
The PCMCIA Card Configuration Registers allow the host to select how
the card is to be addressed. It also allows for other interface
functions, like soft reset.
