R A N G E R 1 8 4 1 P A INTEGRAL
Native| Translation
------+-----+-----+-----
Form PCMCIA TYPE III Cylinders | 977| |
Capacity form/unform 42/ MB Heads 2| 5| |
Seek time / track 18.0/ 8.0 ms Sector/track | 17| |
Controller PCMCIA / ATA Precompensation
Cache/Buffer 32 KB LOOK-AHEAD Landing Zone
Data transfer rate 2.200 MB/S int Bytes/Sector 512
5.000 MB/S ext
Recording method RLL 1/7 operating | non-operating
-------------+--------------
Supply voltage 5 V Temperature *C 5 55 | -40 70
Power: sleep W Humidity % 10 90 |
standby W Altitude km -0.305 3.048| 12.192
idle 0.9 W Shock g 100 | 500
seek W Rotation RPM 3571
read/write 1.5 W Acoustic dBA
spin-up 2.0 W ECC Bit
MTBF h 250000
Warranty Month
Lift/Lock/Park YES Certificates
**********************************************************************
L A Y O U T
**********************************************************************
INTEGRAL RANGER 1841PA PRELIMINARY PRODUCT MANUAL REV. P1 11-92
+----------------------------------------+
| |XX34
| |XX
| |XX
| |XX
| |XX
| |XX
| |XX
| |XX
| |XX
+----------------------------------------+ 1
**********************************************************************
J U M P E R S
**********************************************************************
INTEGRAL RANGER 1841PA PRODUCT MANUAL PRELIMINARY REV. P1, 11-92
Customer Options
----------------
The Model 1841PA can operate as a single drive in a dual drive
configuration. The PCMCIA-ATA specification provides for two card at
a single address through the Twin Card option in the Card Information
Structure (CIS) and card enumeration using the Socket and Copy Re-
gister. When functioning in an ATA configuration, to utilize the
drive as a master, the interface M/-S signal should be connected to
VCC or left open. To configure a drive for use as a second drive or
slave, the interface M/-S signal should be shorted to ground.
**********************************************************************
I N S T A L L
**********************************************************************
INTEGRAL RANGER 1841PA PRODUCT MANUAL PRELIMINARY REV. P1, 11-92
Interface Connector Pin Assignment
----------------------------------
+---+---+--------------------------+-----------------------------+
|Pin|I/O|PCMCIA Memory Signal |PCMCIA I/O Signal |
+---+---+--------------------------+-----------------------------+
| 01| |GND Ground |GND Ground |
+---+---+--------------------------+-----------------------------+
| 02|I/O|D3 Data Bit 3 |D3 Data Bit 3 |
+---+---+--------------------------+-----------------------------+
| 03|I/O|D4 Data Bit 4 |D4 Data Bit 4 |
+---+---+--------------------------+-----------------------------+
| 04|I/O|D5 Data Bit 5 |D5 Data Bit 5 |
+---+---+--------------------------+-----------------------------+
| 05|I/O|D6 Data Bit 6 |D4 Data Bit 6 |
+---+---+--------------------------+-----------------------------+
| 06|I/O|D7 Data Bit 7 |D3 Data Bit 7 |
+---+---+--------------------------+-----------------------------+
| 07|I |CE1- Card Enable |CE1- Card Enable |
+---+---+--------------------------+-----------------------------+
| 08|I |A10 Address Bit 10 |A10 Address Bit 10 |
+---+---+--------------------------+-----------------------------+
| 09|I |OE- Output Enable |OE- Output Enable |
+---+---+--------------------------+-----------------------------+
| 10|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 11|I |A9 Address Bit 9 |A9 Address Bit 9 |
+---+---+--------------------------+-----------------------------+
| 12|I |A8 Address Bit 8 |A8 Address Bit 8 |
+---+---+--------------------------+-----------------------------+
| 13|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 14|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 15|I |WE- Write Enable |WE1 Write Enable |
+---+---+--------------------------+-----------------------------+
| 16|O |RDY/BSY Ready/Busy |IREQ- Interrupt Request |
+---+---+--------------------------+-----------------------------+
| 17|I |Vcc |Vcc |
+---+---+--------------------------+-----------------------------+
| 18|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 19|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 20|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 21|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 22|I |A7 Address Bit 7 |A7 Address Bit 7 |
+---+---+--------------------------+-----------------------------+
| 23|I |A6 Address Bit 6 |A6 Address Bit 6 |
+---+---+--------------------------+-----------------------------+
| 24|I |A5 Address Bit 5 |A5 Address Bit 5 |
+---+---+--------------------------+-----------------------------+
| 25|I |A4 Address Bit 4 |A4 Address Bit 4 |
+---+---+--------------------------+-----------------------------+
| 26|I |A3 Address Bit 3 |A3 Address Bit 3 |
+---+---+--------------------------+-----------------------------+
| 27|I |A2 Address Bit 2 |A2 Address Bit 2 |
+---+---+--------------------------+-----------------------------+
| 28|I |A1 Address Bit 1 |A1 Address Bit 1 |
+---+---+--------------------------+-----------------------------+
| 29|I |A0 Address Bit 0 |A0 Address Bit 0 |
+---+---+--------------------------+-----------------------------+
| 30|I/O|D0 Data Bit 0 |D0 Data Bit 0 |
+---+---+--------------------------+-----------------------------+
| 31|I/O|D1 Data Bit 1 |D1 Data Bit 1 |
+---+---+--------------------------+-----------------------------+
| 32|I/O|D2 Data Bit 2 |D2 Data Bit 2 |
+---+---+--------------------------+-----------------------------+
| 33|O |WP Write Protect |IOIS16- IO Port is 16 bit |
+---+---+--------------------------+-----------------------------+
| 34| |GND Ground |GND Ground |
+---+---+--------------------------+-----------------------------+
| 35| |GND Ground |GND Ground |
+---+---+--------------------------+-----------------------------+
| 36|O |CD1- Card Detect |CD1- Card Detect |
+---+---+--------------------------+-----------------------------+
| 37|I/O|D11 Data Bit 11 |D11 Data Bit 11 |
+---+---+--------------------------+-----------------------------+
| 38|I/O|D12 Data Bit 12 |D12 Data Bit 12 |
+---+---+--------------------------+-----------------------------+
| 39|I/O|D13 Data Bit 13 |D13 Data Bit 13 |
+---+---+--------------------------+-----------------------------+
| 40|I/O|D14 Data Bit 14 |D14 Data Bit 14 |
+---+---+--------------------------+-----------------------------+
| 41|I/O|D15 Data Bit 15 |D15 Data Bit 15 |
+---+---+--------------------------+-----------------------------+
| 42|I |CE2- Card Enable |CE2- Card Enable |
+---+---+--------------------------+-----------------------------+
| 43|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 44|I |N/U Not Used |IORD- IO Read |
+---+---+--------------------------+-----------------------------+
| 45|I |N/U Not Used |IOWR- IO Write |
+---+---+--------------------------+-----------------------------+
| 46|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 47|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 48|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 49|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 50|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 51|I |Vcc |Vcc |
+---+---+--------------------------+-----------------------------+
| 52|I |Vpp2 |Vpp2 |
+---+---+--------------------------+-----------------------------+
| 53|I |N/U Not Used |N/U Not Used |
+---+---+--------------------------+-----------------------------+
| 54|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 55|I |N/U Not Used |N/U Not Used |
+---+---+--------------------------+-----------------------------+
| 56|I |NC |NC |
+---+---+--------------------------+-----------------------------+
| 57|I |N/U Not Used |N/U Not Used |
+---+---+--------------------------+-----------------------------+
| 58|I |RESET Card Reset |RESET Card Reset |
+---+---+--------------------------+-----------------------------+
| 59|O |WAIT- Extend Bus Cycle |WAIT- Extend Bus Cycle |
+---+---+--------------------------+-----------------------------+
| 60|O |N/U Not Used |INPACK- Input Port ACK |
+---+---+--------------------------+-----------------------------+
| 61|I |REG- Register Select |REG- Register Select |
+---+---+--------------------------+-----------------------------+
| 62|O |Logic High |-SPKR |
+---+---+--------------------------+-----------------------------+
| 63|O |Logic High |STSCHG- Change Status |
+---+---+--------------------------+-----------------------------+
| 64|I/O|D8 Data Bit 8 |D8 Data Bit 8 |
+---+---+--------------------------+-----------------------------+
| 65|I/O|D9 Data Bit 9 |D9 Data Bit 9 |
+---+---+--------------------------+-----------------------------+
| 66|I/O|D10 Data Bit 10 |D10 Data Bit 10 |
+---+---+--------------------------+-----------------------------+
| 67|O |CD2- Card Detect |CD2- Card Detect |
+---+---+--------------------------+-----------------------------+
| 68| |GND Ground |GND Ground |
+---+---+--------------------------+-----------------------------+
+---+------------+---+------------+
|Pin|PC CARD-ATA |Pin|PC CARD-ATA |
| |Signal | |Signal |
+---+------------+---+------------+
| 1| GND | 35| GND |
+---+------------+---+------------+
| 2| D3 | 36| -CD1 |
+---+------------+---+------------+
| 3| D4 | 37| D11 |
+---+------------+---+------------+
| 4| D5 | 38| D12 |
+---+------------+---+------------+
| 5| D6 | 39| D13 |
+---+------------+---+------------+
| 6| D7 | 40| D14 |
+---+------------+---+------------+
| 7| -CS0 | 41| D15 |
+---+------------+---+------------+
| 8| NU | 42| -CS1 |
+---+------------+---+------------+
| 9| -ATA | 43| NC |
+---+------------+---+------------+
| 10| NC | 44| -IOR |
+---+------------+---+------------+
| 11| NU | 45| -IOW |
+---+------------+---+------------+
| 12| NU | 46| NC |
+---+------------+---+------------+
| 13| NC | 47| NC |
+---+------------+---+------------+
| 14| NC | 48| NC |
+---+------------+---+------------+
| 15| NU | 49| NC |
+---+------------+---+------------+
| 16| +IRQ | 50| NC |
+---+------------+---+------------+
| 17| VCC | 51| VCC |
+---+------------+---+------------+
| 18| NC | 52| VPP2 |
+---+------------+---+------------+
| 19| NC | 53| NU |
+---+------------+---+------------+
| 20| NC | 54| NC |
+---+------------+---+------------+
| 21| NC | 55| M/-S |
+---+------------+---+------------+
| 22| NU | 56| NC |
+---+------------+---+------------+
| 23| NU | 57| NC |
+---+------------+---+------------+
| 24| NU | 58| RESET |
+---+------------+---+------------+
| 25| NU | 59| IORDY |
+---+------------+---+------------+
| 26| NU | 60| NU |
+---+------------+---+------------+
| 27| A2 | 61| NU |
+---+------------+---+------------+
| 28| A1 | 62| -DASP |
+---+------------+---+------------+
| 29| A0 | 63| -PDIAG |
+---+------------+---+------------+
| 30| D0 | 64| D8 |
+---+------------+---+------------+
| 31| D1 | 65| D9 |
+---+------------+---+------------+
| 32| D2 | 66| D10 |
+---+------------+---+------------+
| 33| -IOCS16 | 67| -CD2 |
+---+------------+---+------------+
| 34| GND | 68| GND |
+---+------------+---+------------+
NU = Not Used
-------------+-----------------------------------------------------
Signal Name |Signal Description
-------------+-----------------------------------------------------
Address Bus |PCMCIA Mode - (Memory and I/O) Signals A0 through A25
|are the host address signals which select a Memory or
|I/O register. A0 is not used in Word-Access Mode.
-------------+-----------------------------------------------------
Data Bus |All modes - Signals D0 through D15 constiture the bi-
|directional data bus.
-------------+-----------------------------------------------------
Card Enable |PCMCIA Mode - (Memory and I/O) CE1 enables transfer
|of even-numbered bytes; CE2, odd-numbered bytes.
-------------+-----------------------------------------------------
Output Enable|PCMCIA Mode - (Memory and I/O) The OE line is the
|active-low signal used to gate Memory Read data from
|the card.
-------------+-----------------------------------------------------
Write Enable |PCMCIA Mode - (Memory and I/O) The WE signal is used
|to strobe Memory Write data into the card.
-------------+-----------------------------------------------------
Ready/Busy |PCMCIA Memory Mode - the Ready/Busy signal is driven
|low to indicate the card is busy and unable to accept
|a Data Transfer operation.
-------------+-----------------------------------------------------
Interrupt |PCMCIA I/O Mode - The Interrupt Request signal is
Request |asserted to indicate to the host that the card
|requires host software service.
-------------+-----------------------------------------------------
Card Detect |All Modes - The -CD1 and -CD2 signals provide
|indication that a card is inserted.
-------------+-----------------------------------------------------
Write Protect|PCMCIA Memory Mode - The WP output signal reflects the
|state of the card's Write Protect switch.
-------------+------------------------------------------------------
IOIS16 bit |PCMCIA I/O Mode - The IOIS16 output signal is
Port |asserted when the IO Port being addressed is capable
|of 16 bit access.
-------------+-----------------------------------------------------
REG |PCMCIA Mode - (Memory and I/O) The -REG signal is
|asserted to select an access to Attribute Memory or
|I/O space.
-------------+-----------------------------------------------------
-STSCHG/ |In the PCMCIA Memory Mapped mode, this line is held
-PDIAG |high. In the PCMCIA I/O mode, this line indicates
|changes in the Ready/-Busy and Write Protect signals
|in the card configuration registers. In the ATA mode,
|this signal indicates to a master that the slave drive
|has passed its internal diagnostic command. During
|reset, this signal is used for master/slave
|communications.
-------------+-----------------------------------------------------
Reset |Reset signal from the host. In the PCMCIA mode this
|signal is active high. In the ATA mode, this signal is
|active low.
-------------+-----------------------------------------------------
-Wait/ |In both PCMCIA and ATA mode, this signal is used to
IORDY |slow down host transfers when the drive is not ready
|to respond.
-------------+-----------------------------------------------------
-INPACK/ |In PCMCIA I/O mode, this signal when enabled is
Not Used |asserted to allow the drive configured by the host.
|In ATA mode, this signal is not used.
-------------+-----------------------------------------------------
SPKR/ |This line is held high in the PCMCIA Memory Mapped
-DASP |mode. In the PCMCIA I/O mode, the DASP signal can be
|enabled to this line using the card configuration re-
|gisters.
|In the ATA mode, this signal is used to drive an LED
|whenever the disk is beeing accessed. This signal is
|active low when the drive is busy. This signal is also
|used to indicate to the master that a slave drive is
|present.
-------------+-----------------------------------------------------
**********************************************************************
F E A T U R E S
**********************************************************************
INTEGRAL RANGER 1841PA PRODUCT MANUAL PRELIMINARY REV. P1, 11-92
Enhanced Ruggedness
-------------------
Notebook, subnotebook and handheld computers used in mobile field
applications must be capable of surviving a high degree of shock and
vibration due to the often unpredictable and adverse conditions
under which they are operated. Int gral's products address these
requirements with a unique ramp loading mechanism for loading and un-
loading the heads without touching the media, providing several
benefits relating to ruggedness, reliability and low power
consumption.
Int gral's dynamic ramp loading technology represents an
innovative approach to solving the environmental challenges of 1.8
inch disk drive engineering by virtually eliminating the possibility
of head slap in the power down state when the drive has been re-
moved from the system. As a result, Int gral's drives can withstand
greater than a 500G shock force in the non-operating mode. The
benefits of ramp loading perhaps can best be illustrated by the
start/stop specification of Int gral drives: a minimum of 250,000
successful start/stops is guaranteed, while a conventional contact
start/stop drive typically specifies only 40,000.
Introduction
------------
The Int gral Model 1841PA is a 1.8 inch ruggedized high performance
disk drive optimized for both PCMCIA-ATA and the ATA standards used
in notebook or palmtop computer. The Model 1841PA can self-configure
for either interface.
Scope
-----
The Model 1841PA interface is based on the interfaces described in
the following reference documents. This manual is intended to high-
light Int gral Peripherals implementation of these interfaces and it
is assumed that the user has a working knowledge of these documents:
CBEMA, ATA, Revision 3.0
PCMCIA, PC Card Standard, Release 2.0
PCMCIA-ATA, Mass Storage Specification, Release 1.0
Key Features
------------
- 1.8 inch form factor hard drive designed to meet the requirements
of a PCMCIA TYPE III PC Card with the exception of dimensions T3.
with integrated PCMCIA Attribute Memory, Card Configuration Re-
gisters and Twin card support.
- Metallic packaging enclosure for ESD protection.
- Automatic sensing of PCMCIA or ATA Host Interface.
- High capacity 1.8 inch providing the lowest power, lowest weight
for the palm top environment.
- Unique ramp loading mechanism for loading and unloading the disk
heads during power downs and periods of inactivity which provides
high shock durability and protection from stiction.
- User invoked low power and power down modes for power sensitive
applications.
- High performance rotary voice coil actuator with embedded servo
system.
- Automatic actuator lock to protect against rotary shock.
- 32K buffer cache with look ahead read.
- Automatic error detection and correction.
Diagnostic Routines
-------------------
Upon power up the microprocessor circuitry of the Model 1841PA per-
forms diagnostics. If an error is detected the drive will not come
ready.
Start Sequence
--------------
When power is applied to the drive, it will interrogate the -OE
signal (pin 9) to determine is the slot is expecting an ATA drive. If
this line is high during this interrogation, the drive interface will
be set to the PCMCIA mode. If this line is low during this interroga-
tion, the drive interface will be set to the ATA mode and remain in
that mode until the next power cycle.
After determining the interface required, the drive will spin up, do
a servo calibration, perform internal diagnostics and come ready.
This requires a total time of 5 seconds. Subsequent spin up from
power saving modes do not require calibration so will be completed
within 1.5 seconds.
Translate Mode
--------------
Since the model 1841PA does not have the same number of sectors on
all cylinders, the drive always functions in the translate mode. Upon
initial power up, the drive will default to 5 heads, 977 cylinders
and 17 sectors per track. The initialize Parameters command can be
used to change these values.
Read Buffer
-----------
The Read Buffer command allows the host to read the current contents
of the drive's sector buffer. Only the Command register is valid for
this command. When this command is issued, the drive will set BSY set
up the sector buffer for a read operation, set the DRQ bit, reset
BSY, and generate an interrupt. The host may then read 512 bytes of
data from the buffer.
Write Buffer
------------
The Write Buffer command allows the host to overwrite the contents of
the drive's sector buffer with any data pattern desired. Only the
Command register is valid for this command. When this command is
issued, the drive will set up the sector buffer for a write operation
and set the DRQ bit. The host may then write 512 bytes of data to the
buffer.
Identify Drive
--------------
The Identify command allows the host to receive parameter information
from the drive. When the command is issued, the drive sets BSY,
stores the required parameter information in the sector buffer, sets
the DRQ bit, resets BSY, and generates an interrupt. The host may
then read the information out of the buffer.
